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description the CXA2027Q is an analog signal processor for ccd linear image sensor output signal. this device is suitable for 3 lines of full-color ccd linear image sensor (ilx516k/ilx518k/ilx520k: 3648 pixels 3 lines/5363 pixels 3 lines/7078 pixels 3 lines). this device has a built-in sample-and-hold, clamp, multiplex, gain control amplifier circuits and can be connected directly with external ad converters. (sony? cxd2311ar, cxd1175am or cxa1977r are recommended as ad converters.) features sample-and-hold circuit pixel-clamp and line-clamp circuit multiplex circuit adc driver circuit gain control amplifier circuit offset control circuit clock frequency: 1.5 to 6mhz (after multiplex) applications color image scanner structure bipolar silicon monolithic ic absolute maximum ratings supply voltage v cc ?.3 to 7 v input voltage v i ?.3 to v cc + 0.3 v output voltage v o ?.3 to v cc + 0.3 v storage temperature tstg ?5 to +150 ? allowable power dissipation p d 640 mw operating conditions (typ. in parentheses) supply voltage v cc 4.75 to 5.25 (5.0) v digital input voltage high v ih 3.5 to v cc (v cc )v digital input voltage low v il 0 to 0.8 (0) v operating temperature topr 0 to +70 ? ?1 CXA2027Q e95210a78 analog signal processor ic sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin qfp (plastic)
?2 CXA2027Q block diagram and pin configuration 25 26 27 28 29 30 36 35 34 31 32 33 2 3 4 5 6 7 8 9 10 11 12 1 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 41 42 43 44 45 46 47 48 latch latch latch d/a d/a d/a log log log dc shift driver gca gca gca gca s/h s/h s/h d/a d/a td4 lclp gc vccp sigout gnd vrt vrb clpc ld4 ld3 ld2 b-in lpr lpg lpb d4-0 vcca d4-1 d4-2 d4-3 d4-4 vccd d5-0 d5-1 d5-2 d5-3 d5-4 d6-0 d6-1 d6-2 d6-3 d6-4 d6-5 ld0 ld1 g-in r-in buf sh mpx2 mpx1 clp td3 td2 td1 td5 td6 v ref d/a
?3 CXA2027Q pin description pin no. 48 1 2 3 4 41 43 44 45 46 5 6 7 8 9 10 symbol (i/o) d5-0 (i) d5-1 (i) d5-2 (i) d5-3 (i) d5-4 (i) d4-0 (i) d4-1 (i) d4-2 (i) d4-3 (i) d4-4 (i) d6-0 (i) d6-1 (i) d6-2 (i) d6-3 (i) d6-4 (i) d6-5 (i) typical pin voltage equivalent circuit description 5-bit data input pin 1 for g channel pixel clamp voltage adjustment (lsb) 5-bit data input pin 2 for g channel pixel clamp voltage adjustment 5-bit data input pin 3 for g channel pixel clamp voltage adjustment 5-bit data input pin 4 for g channel pixel clamp voltage adjustment 5-bit data input pin 5 for g channel pixel clamp voltage adjustment (msb) 5-bit data input pin 1 for b channel pixel clamp voltage adjustment (lsb) 5-bit data input pin 2 for b channel pixel clamp voltage adjustment 5-bit data input pin 3 for b channel pixel clamp voltage adjustment 5-bit data input pin 4 for b channel pixel clamp voltage adjustment 5-bit data input pin 5 for b channel pixel clamp voltage adjustment (msb) 6-bit data input pin 1 for sigout output line clamp voltage adjustment (lsb) 6-bit data input pin 2 for sigout output line clamp voltage adjustment 6-bit data input pin 3 for sigout output line clamp voltage adjustment 6-bit data input pin 4 for sigout output line clamp voltage adjustment 6-bit data input pin 5 for sigout output line clamp voltage adjustment 6-bit data input pin 6 for sigout output line clamp voltage adjustment (msb) lo: 0 to 0.8v hi: 3.5 to 5v lo: 0 to 0.8v hi: 3.5 to 5v dc ac 48 vccd vccd 1.5k 129 100 1.8v vccd vccd 1k 129 100 1.8v 5
?4 CXA2027Q 5-bit data input pin 1 for pre-stage gca gain adjustment (lsb) 5-bit data input pin 2 for pre-stage gca gain adjustment 5-bit data input pin 3 for pre-stage gca gain adjustment 5-bit data input pin 4 for pre-stage gca gain adjustment 5-bit data input pin 5 for pre-stage gca gain adjustment (msb) additional capacitance pin for line clamp. add 0.47f between this pin and gnd. output pin for ad converter reference voltage vrb output pin for ad converter reference voltage vrt gnd pin clpc vrb (o) vrt (o) gnd approx. 3.1v 2.0v 4.0v 0v 16 17 18 19 11 12 13 14 15 ld0 (i) ld1 (i) ld2 (i) ld3 (i) ld4 (i) lo: 0 to 0.8v hi: 3.5 to 5v dc ac vccd vccd 20k 129 11 1.5k vcca 129 16 6.7 1.5k vcca 3k vcca 1k 75 100 vcca 100 vcca 17 6k 2k vcca 100 2.0v vcca 750 100 2k 18 vcca vcca 187.5 4k pin no. symbol (i/o) typical pin voltage equivalent circuit description
?5 CXA2027Q 20 21 22 23 24 25 26 27 28 29 30 31 sigout (o) vccp gc (i) lclp (i) td4 (o) td6 (o) td5 (o) td1 (o) td2 (o) td3 (o) clp (i) mpx1 (i) 5v 0 to 5v 1.7 to 3.6v 2.0 to 3.6v 1.7 to 3.6v 2.0v +max1.8v (2.0 to 3.8v) lo: 0 to 0.8v hi: 3.5 to 5v lo: clamp off hi: clamp on lo: 0 to 0.8v hi: 3.5 to 5v lo: clamp off hi: clamp on lo: 0 to 0.8v hi: 3.5 to 5v signal output pin (to ad converter) power supply pin (for signal output system) voltage input pin for post- stage gca gain adjustment (can be open; in that case outputs 3v) line clamp pulse input pin (apply high level during the optical black period of ccd output) da4 analog output test pin da6 analog output test pin da5 analog output test pin da1 analog output test pin da2 analog output test pin da3 analog output test pin pixel clamp pulse input pin (apply high level during the precharge period of ccd output) mpx channel switching pulse input pin 1 (see high/low table under pin 32 in following section.) (use with open) dc ac vcca vcca 1k 2ma 20 21 100 vcca vcca 20k 129 100 22 4k 30k vcca 1.5k vcca vcca 2k 129 100 1.5v 23 vcca vcca 129 126 24 vcca vcca 1k 129 250 1.5v 30 vcca vcca 1.5k 129 100 1.2v 31 pin no. symbol (i/o) typical pin voltage equivalent circuit description
?6 CXA2027Q mpx channel switching pulse input pin 2. pin 31 pin 32 pin 20 mpx1 mpx2 sigout ll r channel lhg channel hlb channel hhb channel sample-and-hold pulse input pin. (apply low level during the effective signal period (refer to note 1) of ccd output) output test pin after mpx (use with open) ccd signal r channel input pin ccd signal g channel input pin ccd signal b channel input pin 32 33 34 35 36 37 mpx2 (i) sh (i) buf (o) r-in (i) g-in (i) b-in (i) lo: 0 to 0.8v hi: 3.5 to 5v lo: 0 to 0.8v hi: 3.5 to 5v lo: sample mode hi: hold mode dc ac 2.4v +max1.8v (2.4 to 4.2v) ccd effective signal level max1.5vp-p (note 1) vcca vcca 5k 129 130 2.4v 32 1.5k vcca 129 1m 1.5v 33 1m 1.5v 1m 1.5v vcca vcca 2k 260 34 vcca vcca 129 100 3.7v 35 1 pin no. symbol (i/o) typical pin voltage equivalent circuit description
?7 CXA2027Q voltage input pin for setting r channel pre-stage gca gain adjustment latch circuit to data input mode (high) or hold mode (low). voltage input pin for setting g channel pre-stage gca gain adjustment latch circuit to data input mode (high) or hold mode (low). voltage input pin for setting b channel pre-stage gca gain adjustment latch circuit to data input mode (high) or hold mode (low). lo: 0 to 0.8v data hold hi: 3.5 to 5v data input dc ac 38 39 40 42 47 lpr (i) lpg (i) lpb (i) vcca vccd power supply pin (for analog, general system) power supply pin (for da converter system) 5v 5v note 1: effective signal levels are defined as follows for ccd output signals. reset level precharge level effective signal level ccd output signal vccd vccd 1.5k 129 28k 38 fig. 1 pin no. symbol (i/o) typical pin voltage equivalent circuit description
?8 CXA2027Q clamp on clamp off hold mode sample mode output r-ch g-ch b-ch b-ch data input data hold maximum gain minimum gain maximum clamp voltage minimum clamp voltage maximum clamp voltage minimum clamp voltage maximum dc output voltage minimum dc output voltage clamp on clamp off description of data input pin polarity pin name (pin no.) clp(30) sh(33) mpx1/mpx2 (31/32) lpr/lpg/lpb (38/39/40) ld0 to ld4 (11/12/13/14/15) d4-0 to d4-4 (41/43/44/45/46) d5-0 to d5-4 (48/1/2/3/4) d6-0 to d6-5 (5/6/7/8/9/10) lclp(23) pixel clamp high low high low high low 11111 00000 11111 00000 11111 00000 111111 000000 high low lpr: for r-ch lpg: for g-ch lpb: for b-ch ld0: lsb ld4: msb d4-0: lsb d4-4: msb d5-0: lsb d5-4: msb d6-0: lsb d6-5: msb mpx1 low low high high mpx2 low high low high sample-and-hold channel switching for r,g,b channel switching for pre-stage gca gain data input pre-stage gca gain data b-in clamp voltage adjustment g-in clamp voltage adjustment output dc voltage adjustment line clamp function input level characteristics others
?9 CXA2027Q electrical characteristics (see electrical characteristics measurement circuit.) (v cc = 5v, ta = 25?) no. 1 2 3 4 5 6 7 8 9 10 11 12 13 current consumption (1) current consumption (2) digital input voltage high digital input voltage low vrb dc voltage vrt dc voltage vrt-vrb voltage pre-stage gca gain min. pre-stage gca gain max. post-stage gca gain min. post-stage gca gain max. output signal linearity 1 output signal linearity 2 pre and post-stage gca gain = maximum sw11 to 15 = b, sw16 = a, sw22-1 = b, sw22-2 = b, sw23 = a, sw31 to 32 = a, sw35-1 = a pre and post-stage gca gain = minimum sw11 to 15 = a, sw16 = a, sw22-1 = b, sw22-2 = a, sw23 = a, sw31 to 32 = a, sw35-1 = a vrb-vrt equivalent impedance 300 vrb-vrt equivalent impedance 300 vrb-vrt equivalent impedance 300 minimum pre-stage gca gain. input (0.4v) and output (v20) ratio. sw11 to 15 = a, sw16 = a, sw22-1 = a, sw23 = a, sw35-1 = b, sw35-2 = a, sw31, 32 = (a, a) or (a, b) or (b, b) maximum pre-stage gca gain. input (0.4v) and output (v20) ratio. sw11 to 15 = b, sw16 = a, sw22-1 = a, sw23 = a, sw35-1 = b, sw35-2 = a, sw31, 32 = (a, a) or (a, b) or (b, b) minimum post-stage gca gain. input (0.4v) and output (v20) ratio. sw11 to 15 = a, sw16 = a, sw22-1 = b, sw22-2 = a, sw23 = a, sw35-1 = b, sw35-2 = a, sw31 to 32 = a maximum post-stage gca gain. input (0.4v) and output (v20) ratio. sw11 to 15 = a, sw16 = a, sw22-1 = b, sw22-2 = b, sw23 = a, sw35-1 = b, sw35-2 = a, sw31 to 32 = a difference between output value 1/2 level for input level vx and output level for input level 1/2 vx. vx = 1.5v (sg35-2). see note 2. sw11 to 15 = a, sw16 = b, sw22-1 = a, sw23 = b, sw31, 32 = (a, a) or (a, b) or (b, b), sw35-1 = b, sw35-2 = b difference between output value 1/2 level for input level vx and output level for input level 1/2 vx. vx = 0.3v (sg35-2). see note 2. sw11 to 15 = a, sw16 = b, sw22-1 = a, sw23 = b, sw31, 32 = (a, a) or (a, b) or (b, b), sw35-1 = b, sw35-2 = b 44 54 3.5 0 1.96 3.94 1.95 ?.67 11.77 ?.33 3.55 ? ? 60 73 2.00 3.99 1.98 ?.25 13.92 ?.92 5.24 78 94 5 0.8 2.04 4.06 2.05 +1.11 16.03 ?.61 7.12 +5 +5 ma ma v v v v v db db db db % % item measurement conditions min. typ. max. unit symbol icc1 icc2 vih vil vrb vrt vtb gfn gfx grn grx lin1 lin2
?10 CXA2027Q electrical characteristics measurement circuit sw35-1 v20 25 26 27 28 29 30 36 35 34 31 32 33 2 3 4 5 6 7 8 9 10 11 12 1 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 41 42 43 44 45 46 47 48 latch latch latch d/a d/a d/a log log log v ref dc shift driver gca gca gca gca s/h s/h s/h d/a d/a d/a 47 0.01 0.01 5v sw11 sw12 sw13 sw14 sw15 sw16 0.47 v17 v18 1 1 0.01 sw22-1 sw23 sg23 sw32 sw31 3.32v sw35-2 sg35-2 sg35-1 63.6s 7s 0v 5v 63.6s 11.5s 3.32v vx a b sw polarity f = 1mhz 3.12v dc + 0.4vp-p sw22-2 300 3.1v input sg35-2 line clamp pulse sg23 output v20 vx v20 (vx) 4s v20 ( vx) v20 (vx) 1 2 1 2 ? 100 [%]. no. 12 vx = 1.5v no. 13 vx = 0.3v defined as: note 2: no. 12, 13
?11 CXA2027Q pulse timing [pulse timing 1 (pixel units)] clp pulse and sh pulse input the sh pulse at the end of the effective signal so as not to be affected by signal fluctuation caused by the clamp. sh pulse and mpx pulse (mpx1, mpx2) input the sh pulse in sync with the reference channel. mpx1 pulse and mpx2 pulse delay the timing of mpx2 when g changes to b. (table 1, t3) t1 t2 t3 t4 t5 100ns 40ns 5ns 5ns 50ns 20ns 60ns min. typ. max. table 1 brgbr 50% 50% 50% 50% tr = tf = 5ns t1 t3 clp mpx1 mpx2 sigout data taken in at ad converter output channel t2 t5 effective signal level t4 reset level precharge level sh ccd signal (r-in/ g-in/ b-in)
?12 CXA2027Q t6 10s min. typ. max. table 2 the lclp pulse is recommended to be applied during the optical black period. dummy signal aa aa a a a a a a aa aa a a aa aa a a optical black 1-line output period ccd signal (r-in/ g-in/ b-in) lclp t6 [pulse timing 2 (line units)]
?13 CXA2027Q t7 t8 t9 t10 50ns 50ns 50ns 800ns min. typ. max. [pulse timing 3 (latch data input)] t7 t9 t10 (input data decision time) t8 latch gate (lpr/lpg/lpb) input data (ld0 to ld4) table 3
?14 CXA2027Q notes on operation 1. pre-stage gca the gain characteristics is as given in page 16. as a guideline, the calculation formula is 0.5 1.05 n [times] (n = 0 to 31: n is d/a converter input in decimal). 2. post-stage gca the gain characteristics is as given in page 16. when the gc pin is open, gain becomes approximately double. 3. line clamp when the lclp pulse (line clamp pulse) is made high during the optical black period of ccd output, output (pin 20) is clamped approximately to vrb (= 2.0v) voltage. 4. pixel clamp the pixel clamp function (at pins 35, 36 and 37) requires large charging and discharging current through the capacitor, therefore, keep the ground area below the emitter follower as wide as possible. the distance between the input capacitor and input pin should also be as short as possible. 5. dc offset adjustment between channels there is a slight difference between clamp voltages (black level voltage) of different channels due to component scatterings within the ic. correct the b and g channel dc levels relative to r channel using d4-0 to d4-4 and d5-0 to d5-4. the adjustment step for the input pins (pins 36 and 37) is approximately 5mv/lsb. the standard settings are d4-0 to d4-3 = ?? d4-4 = ?? and d5-0 to d5-3 = ?? d5-4 = ?? 6. output dc voltage adjustment output (pin 20) clamp voltage varies slightly due to variations within the ic. adjust output clamp voltage using d6-0 to d6-5. the adjustment step is approximately 1mv/lsb. the standard settings are d6-0, d6-1 = ?? d6-2 to d6-5 = ?? 7. pulse input signals sharp edges at input pulse signals may affect output. if there is a problem, insert a damping resistor (around 100 to 200 ) to smooth the pulse? edges.
?15 CXA2027Q 25 26 27 28 29 30 36 35 31 32 33 2 3 4 5 6 7 8 9 10 11 12 1 13 14 15 16 17 18 20 22 23 24 40 39 38 37 41 43 44 45 46 48 sigout vrt vrb clpc b-in g-in r-in gc td4 sh lclp d4-0 d4-1 d4-2 d4-3 d4-4 d5-0 d5-1 d5-2 d5-3 d5-4 mpx2 mpx1 clp td5 buf td3 td2 td1 lpb td6 gca1 gca2 gca3 gca dc shift driver ref voltage 34 da5 (5bit) da4 (5bit) sw (cont) sh1 sh2 sh3 log log log da1 (5bit) da2 (5bit) da3 (5bit) latch1 latch2 latch3 da6 (6bit) 100 w 2.2k w 12v 100 w 2.2k w 12v 100 w 2.2k w 12v 0.5 to 2.27 0.5 to 2.27 0.5 to 2.27 1 to 3 0.47f vin vrt vrb a/d converter ccd linear image sensor vout-r vout-g vout-b gnd vccp vcca vccd 1000pf 1000pf 1000pf 1f 1f (n.c.) (n.c.) (n.c.) (n.c.) (n.c.) (n.c.) (n.c.) 19 21 42 47 47f 0.1f digital data input pulse input pulse input digital data pulse input digital data input 5v ld4 ld3 ld2 lpr lpg d6-0 d6-1 d6-2 d6-3 d6-4 d6-5 ld0 ld1 application circuit application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?16 CXA2027Q ?0 80 60 40 20 0 ?0 ?0 ?0 0 5 10 15 20 25 30 g, b channels clamp voltage adjustment range d4-0 to d4-4 or d5-0 to d5-4 input data (expressed as decimal system) difference from r channel clamp voltage [mv] ? 12 11 10 9 8 7 6 5 4 3 2 1 0 ? 012345 post-stage gca gain characteristics data (unit) gc pin input voltage [v] gain [db] f = 1mhz ? 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? ? 0 5 10 15 20 25 30 pre-stage gca gain characteristics data (unit) ld0 to ld4 input data (expressed as decimal system) gain [db] 1990 2060 2050 2040 2030 2020 2010 2000 0 102030405060 sigout clamp voltage adjustment range d6-0 to d6-5 input data (expressed as decimal system) sigout voltage [mv] vrb f = 1mhz example of representative characteristics (v cc = 5v, ta = 25?)
?17 CXA2027Q ?.5 2.5 1.5 1 0.5 0 ?.5 ? 01020406070 vrt, vrb temperature characteristics voltage fluctuation temperature [?] fluctuation voltage [mv] 30 50 2 v cc = 5v vrt vrb vrt ?vrb ?.5 2 1.5 1 0.5 0 ?.5 ? 01020 40 6070 clamp voltage temperature characteristics fluctuation temperature [?] sigout fluctuation voltage [mv] 30 50 v cc = 5v sigout sigout ?vrb ?.05 0.3 0.25 0.2 0.15 0.1 0.05 0 01020406070 total gain temperature characteristics fluctuation temperature [?] gain fluctuation [db] 30 50 ld0 to ld4 = 0, gc = open 5v 5.25v 4.75v ?.05 0.15 0.1 0.05 0 4.75 5.25 total gain supply voltage fluctuation vcc [v] gain fluctuation [db] ta = 25? f = 1mhz 5 da1, 2, 3 = all 0/gc = v cc da1, 2, 3 = all 0/gc = open da1, 2, 3 = all 0/gc = gnd da1, 2, 3 = all 1/gc = v cc da1, 2, 3 = all 1/gc = open da1, 2, 3 = all 1/gc = gnd example of temperature and supply voltage fluctuation characteristics
?18 CXA2027Q package outline unit: mm sony code eiaj code jedec code m package structure package material lead treatment lead material package weight epoxy resin solder / palladium plating copper / 42 alloy 48pin qfp (plastic) 15.3 0.4 12.0 ?0.1 + 0.4 0.8 0.3 ?0.1 + 0.15 0.12 13 24 25 36 37 48 112 2.2 ?0.15 + 0.35 0.9 0.2 0.1 ?0.1 + 0.2 13.5 0.15 0.15 ?0.05 + 0.1 qfp-48p-l04 * qfp048-p-1212-b 0.7g note : palladium plating this product uses s-pdppf (sony spec.-palladium pre-plated lead frame).

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